This invention relates to technology for rotating a semiconductor wafer during post copper electroplating processing in a post electrofill module (PEM). More particularly, the invention pertains to wafer chucks used in PEMs to align, rotate and clamp the semiconductor wafer. The modules typically perform a metal etch removing the edge bevel copper, rinse the wafer, and dry the wafer. The PEMs are typically a part of an integrated electrofill modules that includes metal deposition, etching, and any other pre and post treatment.
During integrated circuit fabrication, conductive metal is needed on the active circuit region of the wafer, i.e., the main interior region on the front side, but is undesirable elsewhere. In a typical copper Damascene process, the formation of the desired conductive routes generally begins with a thin physical vapor deposition (PVD) of the metal, followed by a thicker electrofill layer (which is formed by electroplating). The PVD process is typically sputtering. In order to maximize the size of the wafer's useable area (sometimes referred to herein as the “active surface region”) and thereby maximize the number of integrated circuits produced per wafer), the electrofilled metal must be deposited to very near the edge of the semiconductor wafer. Thus, it is necessary to allow physical vapor deposition of the metal over the entire front side of the wafer.
As a byproduct of this process step, PVD metal typically coats the front edge area outside the active circuit region, as well as the side edge, and to some degree, the backside. Electrofill of the metal is much easier to control, since the electroplating apparatus can be designed to exclude the electroplating solution from undesired areas such as the edge and backside of the wafer. One example of plating apparatus that constrains electroplating solution to the wafer active surface is the SABRE™ clamshell electroplating apparatus available from Novellus Systems, Inc. of San Jose, Calif. and described in U.S. Pat. No. 6,156,167, “Clamshell Apparatus For Electrochemically Treating Semiconductor Wafers,” issued to E. Patton et al. on Dec. 5, 2000, which is herein incorporated by reference in its entirety for all purposes.
The PVD metal remaining on the wafer edge after electrofill is undesirable for various reasons. One reason is that PVD metal layers are thin and tend to flake off during subsequent handling, thus generating undesirable particles. This can be understood as follows. At the front side edge of the wafer, the wafer surface is beveled. Here the PVD layers are not only thin, but also unevenly deposited. Thus, they do not adhere well. Adhesion of subsequent dielectric layers onto such thin metal is also poor, thus introducing the possibility of even more particle generation. By contrast the PVD metal on the active interior region of the wafer is simply covered with thick, even electrofill metal and planarized by CMP down to the dielectric. This flat surface, which is mostly dielectric, is then covered with a barrier layer substance such as SiN that both adheres well to the dielectric and aids in the adhesion of subsequent layers.
Wafer chucks have been designed that can hold the semiconductor wafer during the metal etch. The system may align the wafer on chuck for rotation. Conventionally, such alignment is done by placing the wafer on the chuck that has a self-aligning capability or in a separate alignment module and then transporting it the chuck. The wafer chuck does not contact the wafer edges during the actual etching of unwanted metal from those regions. Otherwise, the viscous etchant would not be able to flow over the side edge of the wafer unimpeded. During rinsing and drying, the wafer may rotate at high-speeds, at which time the wafer is preferably constrained to the wafer chuck. Such a wafer chuck is described in U.S. Pat. No. 6,537,416 issued to Mayer et al. on Mar. 25, 2003, U.S. Pat. No. 6,967,174 issued to Mayer et al. on Nov. 22, 2005, both titled “Wafer Chuck For Use In Edge Bevel Removal of Copper From Silicon Wafers” and are incorporated by reference herein in its entirely for all purposes. The wafer chuck is also described in U.S. patent application Ser. No. 11/248,874, filed Oct. 11, 2005, titled “Edge Bevel Removal of Copper From Silicon Wafers,” which is incorporated by reference herein in its entirely for all purposes.
However, some problems have been observed with the process using the wafer chuck. The edge exclusion (EE), the portion of the wafer etched during EBR, has been observed to vary at different locations of the wafer. Irregularity of the etchant stream may cause this variation. At times, this EE variation manifests as a wave in the copper around the edge, caused by incomplete removal in some areas. Another problem is particles transfer to the wafer by the mechanical action of the tool. Tool availability may be reduced by adders such as particles, droplets, streaks, or any other contamination that can be entrained and transported to the wafer surface because the test is re-run until the cleanliness reduces to some prescribed level.
Therefore, an improved wafer chuck design is desirable.